圖書信息
叢書名： 經典原版書庫
作 者： （美）羅恩 著
出 版 社： 機械工業出版社
出版時間： 2005-9-1
版 次： 1
頁 數： 453
開 本： 16
印 次： 1
紙 張： 膠版紙
I S B N ： 9787111171935
包 裝： 平裝
所屬分類： 圖書 >> 計算機/網路 >> 計算機理論
定價：￥55.00
內容簡介
本書利用Tensilica公司的Xtensa結構和TIE語言，系統地闡明了以處理器為核心進行設計的問題、機遇和挑戰。Rowen介紹了一種全新的設計方法，然後介紹了其基本技術：處理器配置、擴展、硬體/軟體協同生成、多處理器劃分/通信等。
內容摘要
●為什麼可擴展的處理器是必需的：當前設計方法有什麼缺點。
●將可擴展的處理器結構與傳統的處理器及硬連線邏輯電路相比較。
●延遲、吞吐率、並行功能的協調、硬體互連選擇、設計複雜度的管理等問題。
●針對嵌入式系統的多處理器SoC結構。
●從軟體和硬體開發者角度觀察的任務設計。
●先進的技術：實現複雜的狀態機、任務-任務之間的同步、功率最佳化等。
作者簡介
Chris Rowen博士 Tensilica公司 (在高產量系統中，該公司在使用專用微處理器的自動生成方面居於領先地位) 的總裁、CEO和創始人。他在史丹福大學參與了RISC結構的最初研發工作，幫助創建了MIPS Computer Systems公司，並曾在Synopsys公司任Design Reuse Group (設計復用集團) 的副總裁和總經理。他擁有史丹福大學的電氣工程學博士學位。
圖書目錄
1. The Case for a New SOC Design Methodology
1.1 The Age of MegagateSOCS
1.2 The Fundamental Trends of SOC Design
1.3 What’s Wrong with Today’s Approach to SOC Design?
1.4 Preview: An Improved Design Methodology for SOC Design
1.5 Further Reading
2. SOC Design Today
2.1 Hardware System Structure
2.2 Software Structure
2.3 Current SOC DesignFlow
2.4 The Impact of Semiconductor Economics
2.5 Six Major Issues in SOC Design
2.6 Further Reading.
3. ANEW LOOKat SOC Design
3.1 Accelerating Processors for Traditional Software Tasks
3.2 Example: Tensilica Xtensa Processors forEEMBCBenchmarks
3.3 System Design with Multiple Processors
3.4 New Essentials of SOC Design Methodoloy
3.5 Addressing the Six Problems
3.6 Further Reading
4. System-Level Design of Complex SOCs
4.1 Complex SOC System Architecture Opportunities
4.2 Major Decisions in Processor-Centric SOC Organization
4.3 Communication Design = Software Mode + Hardware Interconnect
4.4 Hardware Interconnect Mechanisms
4.5 Performance-Driven Communication Design
4.6 The SOC Design Flow
4.7 Non-Processor Building Blocks in Complex SOC
4.8 Implications of Processor-Centric SOC Architecture
4.9 Further Reading
5. Configurable Processors: A Software View
5.1 Processor Hardware/Software Cogeneration
5.2 The Process of Instruction Definition and Application Tuning
5.3 The Basics of Instruction Extension
5.4 The Programmer’s Mode
5.5 Processor Performance Factors
5.6 Example: Tuning a Large Task
5.7 Memory-System Tuning
5.8 Long Instruction Words
5.9 Fully Automatic Instruction-Set Extension
5.10 Further Reading
6. Configurable Processors: A Hardware View
6.1 Application Acceleration: A Common Problem
6.2 Introduction to Pipelines and Processors
6.3 Hardware Blocks to Processors
6.4 Moving from Hardwired Engines to Processors
6.5 Designing the Processor Interface
6.6 A Short Example: ATM Packet Segmentation and Reassembly
6.7 Novel Roles for Processors in Hardware Replacement
6.8 Processors, Hardware Implementation, and Verification Flow
6.9 Progress in Hardware Abstraction
6.10 Further Reading
7. Advanced Topics in SOC Design
7.1 Pipelining for Processor Performance
7.2 Inside Processor Pipeline Stalls
7.3 Optimizing Processors to Match Hardware
7.4 Multiple Processor Debug and Trace
7.5 Issues in Memory Systems
7.6 Optimizing Power Dissipation in Extensible Processors
7.7 Essentials of TIE
7.8 Further Reading
8. The Future of SOC Design: The Sea of Processors
8.2 Why Is Software Programmability So Central?
8.3 Looking into the Future of SOC
8.4 Processor Scaling Model
8.5 Future Applications of Complex SOCs
8.6 The Future of the Complex SOC Design Process
8.7 The Future of the Industry
8.8 The Disruptive-Technology View
8.9 The Long View
8.10 Further Reading
Index
