簡介
韓銀和主要研究：容錯和低功耗體系結構，互連體系結構。他已發表了20餘篇SCI檢索論文，40餘篇EI檢索論文，授權專利10項。他連續2年（2010，2011）在體系結構頂級會議ISCA上發表論文，在IEEE Trans on Computer等IEEE/ACM期刊上發表論文10餘篇。他博士論文期間從事積體電路測試壓縮研究，由於工作突出，他獲得了中科院院長優秀獎、特別獎（各一項），中科院優秀博士論文，計算機學會優秀博士論文，全國百篇優秀博士論文提名（獎）。和同事一起，獲得了北京市科學技術獎2項，中國計算機學會王選獎。
工作經歷
2014年-，中科院計算所(計算機體系結構國家重點實驗室),研究員
2008年9月-2014年，中科院計算所(系統結構重點實驗室),副研究員
2006年3月-2008年9月，中科院計算所(先進測試技術實驗室),助理研究員
所屬部門
計算機體系結構國家重點實驗室
研究興趣
積體電路設計與測試、計算機容錯結構設計，可重塑處理器
主持的科研項目
1.863探索類項目，“大規模多核處理器系統片上高性能互連技術研究”， 在研
2.國家自然科學基金面上項目，“片上網路晶片中路由器和互連線的測試方法研究”，在研
3.863探索類項目（副組長），“多處理器片上系統運行中低功耗關鍵技術研究”，在研
4.NSFC與香港RGC聯合科研基金項目（陸方合作申請人之一），“片上系統測試架構設計與最佳化：針對噪聲引起的測試良產率下降的研究”，在研
論文著作
國際會議論文
2013
[C33]Hang Lu, Guihai Yan, Yinhe Han, Binzhang Fu, Xiaowei Li, “RISO: Relaxed Network-on-Chip Isolation for Cloud Processors”, Proc. of Design Automation Conference (DAC), 2013. (PDF)
2012
[C32] Guihai Yan, Yingmin Li, Yinhe Han, Xiaowei Li, Minyi Guo, Xiaoyao Liang, "AgileRegulator: A Hybird Voltage Regulator Scheme Redeeming Dark Silicon for Power Efficiency in a Multicore Architecture", Proc. of High Performance Computer Architecture(HPCA), 2012. (PDF)
2011
[C31] Binzhang Fu, Yinhe Han, Jun Ma, Huawei Li, Xiaowei Li, "An Abacus Turn Model for Time/Space-Efficient Reconfigurable Routing", Proc. of IEEE/ACM International Symposium on Computer Architecture (ISCA), 2011. (PDF)
[C30] Jianbo Dong, Lei Zhang, Yinhe Han, Xiaowei Li, “Wear Rate Leveling: Lifetime Enhancement of PRAM with Endurance Variation”, Proc. of IEEE/ACM Design Automation Conference (DAC), 2011.(PDF)
[C29] Jianliang Gao, Yinhe Han, Xiaowei Li, “Avoiding Data Repetition and Data Loss in Debugging Multiple-Clock Chips”, Will appear in Proc. of IEEE/ACM Design, Automation, and Test in Europe (DATE), 2011.(PDF)
[C28] Ying Wang, Lei Zhang, Yinhe Han, Huawei Li and Xiaowei Li, “Smart Memory: exploiting and managing abundant off-chip optical bandwidth”, Will appear in Proc. of IEEE/ACM Design, Automation, and Test in Europe (DATE), 2011. (PDF)
[C27] Cheng Liu, Lei Zhang, Yinhe Han, Xiaowei Li, “Vertical Interconnects Squeezing in Symmetric 3D Mesh Network-on-Chip”, Will appear in Proc. of Asia and South Pacific Design Automation Conference (ASP-DAC), 2011.(PDF)
[C26] Cheng Liu, Lei Zhang, Yinhe Han, Xiaowei Li, “A Resilient On-chip Router Design Through Data Path Salvaging”, Will appear in Proc. of Asia and South Pacific Design Automation Conference (ASP-DAC), 2011.(PDF)
2010
[C25] Huawei Li, Dawen Xu, Yinhe Han, Kwang-Ting Cheng and Xiaowei Li, “nGFSIM : A GPU-Based Fault Simulator for 1-to-n Detection and its Applications”, Proc. of IEEE International Test Conference (ITC), paper 12.1, Nov. 2010.(PDF)
[C24]Song Jin, Yinhe Han, Huawei Li and Xiaowei Li, “P2CLRAF: An Pre- and Post-silicon Cooperated Circuit Lifetime Reliability Analysis Framework”, Proc. of IEEE Asian Test Symposium (ATS), 2010. (PDF)
[C23]Ying Wang, Lei Zhang, Yinhe Han, Huawei Li and Xiaowei Li, “Address Remapping for Static NUCA in NoC-based Degradable Chip-Multiprocessors”, Proc. of IEEE Pacific Rim International Symposium on Dependable
Computing (PRDC), 2010. (PDF)
[C22] Guihai Yan, Xiaoyao Liang, Yinhe Han, Xiaowei Li , “Leveraging the Core-Level Complementary Effects of PVT Variations to Reduce Timing Emergencies in Multi-Core Processors”, Proc. of IEEE/ACM International Symposium on Computer Architecture (ISCA), 2010. (PDF)
[C21] Bingzhang Fu, Yinhe Han, Huawei Li, Xiaowei Li , “Binary-Tree Waveguide Connected Time/Power Efficient Optical Network-on-Chip”, Proc. of IEEE/ACM Design, Automation, and Test in Europe (DATE), 2010. (PDF)
[C20] Lei Zhang, Yu Yue, Yinhe Han, Xiaowei Li, Shangping Ren ,”Performance-Asymmetry-Aware Topology Virtualization for Defect-tolerant NoC-Based Many-core Processors”, Proc. of IEEE/ACM Design, Automation, and Test in Europe (DATE), 2010.(PDF)
2009
[C19] Jun Liu, Yinhe Han, Xiaowei Li , “Extended Selective Encoding of Scan Slices for Reducing Test Data and Test Power”, Proc. of IEEE Asian Test Symposium (ATS), 2009.
[C18] Song Jin, Yinhe Han, Lei Zhang, Huawei Li , Xiaowei Li and Guihai Yan,” M-IVC: Using Multiple Input Vectors to Minimize Aging-induced Delay”, Proc. of IEEE Asian Test Symposium (ATS), 2009.(PDF)
[C17] Jianbo Dong, Lei zhang, Yinhe Han, Guihai Yan and Xiaowei Li , “Variation-Aware Scheduling for Chip Multiprocessors with Thread Level Redundancy”, Proc. of IEEE Pacific Rim International Symposium on Dependable Computing (PRDC), 2009.(PDF)
[C16] Bingzhang Fu, Yinhe Han, Huawei Li and Xiaowei Li ,”A New Multiple-Round DOR Routing for 2D Network-on-chip Meshes”,Proc. of IEEE Pacific Rim International Symposium on Dependable Computing (PRDC), 2009.(PDF)
[C15] Guihai Yan, Yinhe Han, Hui Liu, Xiaoyao Liang, Xiaowei Li, "MicroFix: Exploiting Path-grained Timing Adaptability for Improving Power-Performance Efficiency", International Symposium on Low Power Electronics and Design(ISLPED), 2009.(PDF)
[C14] Guihai Yan, Yinhe Han, Xiaowei Li, “A Unified Online Fault Detection Scheme via Checking of Stability Violation”, Design, Automation and Test in Europe 2009. (PDF)
[C13] Jianliang Gao, Yinhe Han, and Xiaowei Li, "A New Post-silicon Debug Approach Based on Suspect Window", VLSI Test Symposium(VTS), 2009. (PDF)
2008
[C12] Lei Zhang, Yinhe Han, Qiang Xu, and Xiaowei Li, “Defect Tolerance in Homogeneous Manycore Processors Using Core-Level Redundancy with Unified Topology,” IEEE/ACM Design, Automation and Test in Europe (DATE), pp. 891-896, 2008. (PDF)
2007
[C11] Lei Zhang, Yinhe Han, Qiang Xu, and Xiaowei Li, “Topology Reconfiguration Problem for Core-Level Redundancy in Homogeneous Chip Many-core Processors,” Fast Abstract, IEEE/IFIP International Conference on Dependable System and Networks (DSN), pp. 364-365, 2007. (PDF)
[C10] Shaohua Lei, Yinhe Han, Xiaowei Li, "Frequency Analysis Model for Propagation of Transient Errors in Combinational Logic", Proc. of IEEE Asian Test Symposium (ATS), Oct. 2007, Beijing, pp.223-228. (PDF)
2006
[C9] Tong Liu, Huawei Li, Xiaowei Li, and Yinhe Han, “Fast Packet Classification using Group Bit Vector”, Proc. of 49th Annual IEEE Global Telecommunications Conference (Globecom2006), pp.1-5, 2006. (PDF)
[C8]Jie Dong, Yu Hu, Yinhe Han, Xiaowei Li, “An On-chip Combinational Decompressor for Reducing Test Data Volume”, Proc. of IEEE International Symposium on Circuits and Systems (ISCAS'06), May 21-24, 2006, Greece, pp.1459-1462
2005
[C7] Yinhe Han, Yu Hu, Xiaowei Li, and Huawei Li, “Using MUXs Network to Hide Bunches of Scan Chains,” in Proc. IEEE/ACM International Symposium on Quality Electronic Design (ISQED), pp. 238-243, May 2005. (PDF)
[C6] Yinhe Han, Yu Hu, Huawei Li, and Xiaowei Li, “Theoretic Analysis and Enhanced X-Tolerance of Test Response Compact based on Convolutional code,” in Proc. IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), pp. 53-58, January 2005. (PDF)
[C5] Ji Li, Yinhe Han, Xiaowei Li, “Deterministic and Low Power BIST Based on Scan Slice Overlapping”, Proc. of IEEE of International Symposium on Circuits and Systems (ISCAS), May 2005, Kobe, Japan, pp.5670-5673. (PDF)
2004
[C4] Yinhe Han, Yu Hu, Anshuman Chandra, Huawei Li, and Xiaowei Li, “Rapid and Energy-Efficient testing for Embedded Cores,” in Proc. IEEE Asian Test Symposium, pp. 8-13, November 2004. (EI Access: 05078836557) (PDF)
[C3] Yinhe Han, Yongjun Xu, Huawei Li, Xiaowei Li, and Anshuman Chandra, “Response Compaction for Test Time and Test Pins Reduction Based on Advanced Convolutional Codes,” in Proc. IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 298-305, Cannes, France, October 2004.(EI Access: 05399379765) (PDF)
[C2] Yu Hu, Yinhe Han, Huawei Li, Tao Lv, Xiaowei Li, “Pair Balance-Based Test Scheduling for SOCs”, Proc. of IEEE 13th Asian Test Symposium (ATS'04) , Kenting, November 15-17, 2004, pp.236-241. (PDF)
2003
[C1] Yinhe Han, Yongjun Xu, Anshuman Chandra, Huawei Li, and Xiaowei Li, “Test Resource Partitioning Based on Efficient Response Compaction for Test TArime and Tester Channel Reduction,” in Proc. IEEE Asian Test Symposium, pp. 440-445, November 2003. (PDF)
國際刊物論文
2012
[J24] Song Jin, Yinhe Han, Huawei Li, Xiaowei Li, "Unified Capture Scheme for Small Delay Defect Detection and Aging Prediction", IEEE Transactions on Very Large Scale Integration(VLSI) Systems, 2012. (PDF)
[J23]Yuanqing Cheng, Lei Zhang, Yinhe Han, Xiaowei Li, "Thermal-Constrained Task Allocation for Interconnect Energy Reduction in 3-D Homogeneous MPSoCs", IEEE Transactions on Very Large Scale Integration(VLSI) Systems, 2012. (PDF)
2011
[J22] Guihai Yan, Yinhe Han, Hui Liu, Xiaoyao Liang, Xiaowei Li, "MicroFix: Using Timing Interpolation and Delay Sensors for Power Reduction", ACM Transactions on Design Automation of Electronic Systems, 16(2), Artical 16, 2011. (PDF)
[J21] Guihai Yan, Yinhe Han, Xiaowei Li, "ReviveNet: A Self-Adaptive Architecture for Improving Lifetime Reliability via Localized Timing Adaptation", IEEE Transactions on Computers, 60(9), pp. 1219-1231, 2011. (PDF)
2010
[J20]Jianbo Dong, Lei Zhang, Yinhe Han, Guihai Yan and Xiaowei Li, “Performance-asymmetry-aware scheduling for Chip Multiprocessors with static core coupling”, Journal of Systems Architecture, 56, 534-542, 2010.
[J19] Jianliang Gao, Yinhe Han, Xiaowei Li, “A Novel Post-Silicon Debug Mechanism Based on Suspect Window”, IEICE Transactions on Information and Systems, Vol.E93-D No.5 pp.1175-1185, 2010.
[J18] Jun Liu, Yinhe Han, Xiaowei Li, “Extended Selective Encoding for Reducing Test Data and Test Power”, IEICE Transactions on Information and Systems ,Vol.E93-D No.8, pp.2223-2232，2010.
2009
[J17] Lei Zhang, Yinhe Han, Qiang Xu, Xiaowei Li and Huawei Li. “On Topology Reconfiguration for Defect-Tolerant NoC-Based Homogeneous Manycore Systems”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.17, pp.1173-1186, 2009. (PDF)
[J16] Wei Wang, Yin-He Han, Xiao-Wei Li, Fang Fang. “Co-optimization of Dynamic/Static Test Power in Scan Test”, Chinese Journal of Electronics. (PDF)
2008
[J15] Guihai Yan, Yinhe Han, Xiaowei Li, and Hui Liu, “BAT: Performance-Driven Crosstalk Mitigation Based on Bus-grouping Asynchronous Transmission,” IEICE Transactions on Electronic,E91-C(10), pp. 1690-1697, 2008. (PDF)
2007
[J14] Yinhe Han, Yu Hu, Xiaowei Li, Huawei Li, and Anshuman Chandra, “Embedded Test Decompressor to Reduce the Required Channels and Vector Memory of Tester for Complex Processor Circuit,” IEEE Transactions on Very Large Scale Integration Systems, Vol. 15, No. 5, pp. 531-540, May 2007. (PDF)
[J13] Wang Wei, Hu Yu, Han Yinhe, Li Xiaowei, Zhang Yousheng，“Leakage Current Optimization Techniques during Test based on Don’t Care Bits Assignment，”Journal of Computer Science and Technology, Vol. 22, No. 5, pp. 673-680, 2007. (PDF)
[J12] Lei Zhang, Yinhe Han, Huawei Li, Xiaowei Li, "A Fault Tolerance Mechanism in Chip Many-core Processors", Tsinghua Science and Technology, Vol.12, No.S1, July 2007, pp.169-174. (PDF)
2006
[J11] Yinhe Han, Xiaowei Li, Huawei Li, and Anshuman Chandra, “Embedded Test Resource for SoC to Reduce Required Tester Channels Based on Advanced Convolutional Codes,” IEEE Transactions on Instrumentation and Measurement, Vol. 55, No. 2, pp. 389-399, April 2006. (SCI IDS: 026IB, EI Access: 06149794655) (PDF)
[J10] Yinhe Han, Huawei Li, Xiaowei Li, and Anshuman Chandra, “Response Compaction for Test Time and Required TAM Width Reduction Based on Advanced Convolutional Codes,” Science In China: Serial F, Vol. 49, No.2, pp. 262-272, April 2006. (PDF)
[J9] Yu Hu, Yinhe Han, Xiao Li, Huawei Li, and Xiaoqing Wen, “Compression/Scan Co-Design for Reducing Test Data Volume, Scan-in Power Dissipation, and Test Application Time Received,” IEICE Transactions on Information and Systems, Vol. E89-D, No. 10, pp.2616-2625, Oct. 2006. (PDF)
[J8] Wei Wang, Yinhe Han, Xiaowei Li, Yousheng Zhang, "Techniques of Leakage Current Optimization Based on Don't Care Bits in Test Vectors ", ACTA Electronica Sinica, Vol. 34, No. 2, pp.282-286, 2006. (in Chinese)
[J7] Jie Dong, Yu Hu, Yinhe Han, Xiaowei Li, "A Multiple-Scan-Chain Test Approach Based on Combinational Decompression Circuits ", JournalL of Computer Research and Development, Vol. 43, No. 6, pp.1001-1007, 2006. (in Chinese)
[J6] Yu Hu, Yinhe Han, Xiaowei Li, "Design-for-Testability and Test Technologies for System-on-a-Chip ", Journal of Computer Research and Development, Vol. 42, No. 1, pp.153-162, 2006. (in Chinese)
2005
[J5] Yinhe Han, Yu Hu, Xiaowei Li, Huawei Li, Anshuman Chandra, and Xiaoqing Wen, “Wrapper Scan Chains Design for Rapid and Low Power Testing of Embedded Cores,” IEICE Transactions On Information and Systems, Vol. E88-D, No.9, pp. 2126-2134, Sept. 2005. (SCI IDS: 967HJ, EI Access: 05429418698). (PDF)
[J4] Yinhe Han, Yongjun Xu, Anshuman Chandra, Huawei Li, and Xiaowei Li, “Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Tester Channels Reduction,” Journal of Computing Science and Technology (JCST), pp. 201-210,20(2), Feb. 2005. (SCI IDS: 910GN,EI Access: 05209106292) (PDF)
[J3] Yongjun Xu, Yinhe Han, Huawei Li, Xiaowei Li, "Power Sensitivity Analysis of Combinational Circuits Using Statistical Method ", Journal of Computer-Aided Design & Computer Graphics, Vol. 17, No. 1, pp.122-128, 2005. (in Chinese)
2004
[J2] Yinhe Han, Xiaowei Li, Yongjun Xu, Huawei Li, "Test Resource Partitioning Using Variable-Tail Code ", ACTA Electronica Sinica, Vol. 32, No. 8, pp.1346-1350, 2004. (in Chinese)
[J1] Yongjun Xu, Yinhe Han, Zuying Luo, Xiaowei Li, "Maximum Power-up Current Estimation Based on Genetic Algorithm ", Chinese Journal of Computers, Vol. 27, No. 2, pp.186-191, 2004. (in Chinese)
Workshop
2009
[W7] Dawen Xu, Yinhe Han, Huawei Li and Xiaowei Li, “A Fast and Memory-Efficient Fault Simulation Using GPU”, IEEE 10th Workshop on RTL and High Level Testing, 2009.
[W6] Song Jin, Yinhe Han, Lei Zhang, Huawei Li and Xiaowei Li, “On Predicting the Maximum Circuit Aging”, IEEE 10th Workshop on RTL and High Level Testing, 2010.
[W5] Jun Liu, Yinhe Han, Xiaowei Li ,"Scan Slices Compression Technique Using Dynamical Updating Reference Slices", IEEE 10th Workshop on RTL and High Level Testing, 2009.
2008
[W4] Yinhe Han, Fang Fang, Wei Wang, Jianbo Dong, Xiaowei Li, Shanlin Yang, “Multicast Testing Method for NoC-based SoC Using Test Branches” IEEE 9th Workshop on RTL and High Level Testing, pp. 1-6, 2008. (PDF)
[W3] Binzhang Fu, Yinhe Han, Huawei Li and Xiaowei Li, “A New Methodology of reusing Network-on-Chip as Test-Access-Mechanism,” 2nd Workshop on Diagnostic Services in Network-on-Chips, pp.245-278, 2008. (PDF)
2007
[W2] Guihai Yan, Yinhe Han, Xiaowei Li, Hui Liu, "Performance-Driven Crosstalk Mitigation Based on Bus-Grouping Transmission", Digest of Papers, IEEE 8th Workshop on RTL and High-Level Testing (WRTLT'07), October 12-13, Beijing, pp.119-124. (PDF)
2006
[W1] Wei Wang, Yinhe Han, Xiaowei Li, Yousheng Zhang, Yu Hu and Huawei Li, “PowerCut- A Novel Low-power scan testing”, Digest of Papers, IEEE 7th Workshop on RTL and High-Level Testing (WRTLT’06), July 23-24, 2006, Fukuoka, Japan, pp.49-54. (PDF)
獎勵
2006年 中國科學院院長獎學金特別獎。
2005年 中國計算機學會創新獎“積體電路邏輯測試基礎技術”（排名第三）
2003年 IEEE Asia Test Symposium最佳論文獎（IEEE Test Technology Technical Council 頒發）。
2005年 IEEE/ACM Asian South Pacific Design Automation Conference最佳論文獎提名，測試領域唯一。
2005年 獲“中國科學院計算技術研究所所長特別獎”。
2005年 中國科學院計算技術研究所SONY獎。
專利
1. 韓銀和、李曉維，“一種單輸出無反饋時序測試影響壓縮電路”，專利號：ZL031490743, 授權日：2006年9月27日。
2. 韓銀和，李曉維，“用於交流掃描測試中的片上快速信號生成電路”，專利號：ZL200410004831. 2，授權時間：2008年3月5日。
3. 韓銀和，李曉維，“一種快速的積體電路測試流程最佳化方法”，專利號：ZL200410006727. 7，授權時間：2007年8月8日。
4. 韓銀和，李曉維，“一種卷積碼的編碼方法” ，專利號：ZL200410045981. 8，授權時間：2008年2月6日。
5. 韓銀和，李曉維，“一種套用於系統級晶片測試中的芯核並行包裝電路和方法”， 專利號：ZL200410047572. 1，授權時間：2007年6月27日。
