數字邏輯與Verilog設計（第3版）

《數字邏輯與Verilog設計（第3版）》是2014年清華大學出版社出版的圖書。

圖書簡介

本書共包括11章正文和兩篇附錄。為了讓讀者了解傳統的人工進行數字設計的基本理論，前六章主要還是介紹數字邏輯的基礎，且此部分內容可以作為一個學期的數字邏輯設計導論課程。由於數字系統的規模越來越大，採用計算機輔助設計工具來完成數字電路的設計勢在必行，因此本書從第2章開始就將相關知識融入到基礎理論中，讓讀者能在閱讀和學習過程中潛移默化地掌握Verilog代碼編寫風格，達到事半功倍的效果。

目錄

Chapter 1Introduction1

1.1Digital Hardware2

1.1.1Standard Chips4

1.1.2Programmable Logic Devices5

1.1.3CustomDesigned Chips5

1.2The Design Process6

1.3Structure of a Computer8

1.4Logic Circuit Design in This Book8

1.5Digital Representation of Information11

1.5.1Binary Numbers12

1.5.2Conversion between Decimal and

Binary Systems13

1.5.3ASCII Character Code14

1.5.4Digital and Analog Information16

1.6Theory and Practice16

Problems18

References19

Chapter 2Introduction to Logic

Circuits21

2.1Variables and Functions22

2.2Inversion25

2.3Truth Tables26

2.4Logic Gates and Networks27

2.4.1Analysis of a Logic Network29

2.5Boolean Algebra33

2.5.1The Venn Diagram37

2.5.2Notation and Terminology42

2.5.3Precedence of Operations43

第1章緒論1

1.1數字硬體2

1.1.1標準晶片4

1.1.2可程式邏輯器件5

1.1.3定製晶片5

1.2設計過程6

1.3計算機結構8

1.4本書中的邏輯電路設計8

1.5信息的數字表示11

1.5.1二進制數12

1.5.2十進制和二進制系統之間的

轉換13

1.5.3ASCII字元碼14

1.5.4數字和模擬信息16

1.6理論和實踐16

習題18

參考文獻19

第2章邏輯電路導論21

2.1變數和函式22

2.2反相25

2.3真值表26

2.4邏輯門和網路27

2.4.1邏輯網路的分析29

2.5布爾代數33

2.5.1維恩圖37

2.5.2符號和術語42

2.5.3操作的優先權43

2.6Synthesis Using AND, OR, and NOT

Gates43

2.6.1SumofProducts and Productof

Sums Forms48

2.7NAND and NOR Logic Networks54

2.8Design Examples59

2.8.1ThreeWay Light Control59

2.8.2Multiplexer Circuit60

2.8.3Number Display63

2.9Introduction to CAD Tools64

2.9.1Design Entry64

2.9.2Logic Synthesis66

2.9.3Functional Simulation67

2.9.4Physical Design67

2.9.5Timing Simulation67

2.9.6Circuit Implementation68

2.9.7Complete Design Flow68

2.10Introduction to Verilog68

2.10.1Structural Specification of Logic

Circuits70

2.10.2Behavioral Specification of Logic

Circuits72

2.10.3Hierarchical Verilog Code76

2.10.4How NOT to Write Verilog Code78

2.11Minimization and Karnaugh Maps78

2.12Strategy for Minimization87

2.12.1Terminology87

2.12.2Minimization Procedure89

2.13Minimization of ProductofSums Forms91

2.14Incompletely Specified Functions94

2.15MultipleOutput Circuits96

2.16Concluding Remarks101

2.17Examples of Solved Problems101

Problems111

References120

2.6用與、或和非門進行綜合43

2.6.1與或和或與形式48

2.7與非和或非邏輯網路54

2.8設計實例59

2.8.1三路燈光控制59

2.8.2多路選擇器電路60

2.8.3數字顯示63

2.9CAD工具簡介64

2.9.1設計輸入64

2.9.2邏輯綜合66

2.9.3功能仿真67

2.9.4物理設計67

2.9.5時序仿真67

2.9.6電路實現68

2.9.7完整的設計流程68

2.10Verilog簡介68

2.10.1邏輯電路的結構描述70

2.10.2邏輯電路的行為描述72

2.10.3層次化Verilog代碼76

2.10.4如何不寫Verilog代碼78

2.11化簡和卡諾圖78

2.12化簡策略87

2.12.1術語87

2.12.2化簡過程89

2.13或與形式的最簡91

2.14不完全確定函式94

2.15多輸出電路96

2.16小結101

2.17問題求解案例101

習題111

參考文獻120

Chapter 3Number Representation and

Arithmetic Circuits121

3.1Positional Number Representation122

3.1.1Unsigned Integers122

3.1.2Octal and Hexadecimal

Representations123

3.2Addition of Unsigned Numbers125

3.2.1Decomposed FullAdder129

3.2.2RippleCarry Adder129

3.2.3Design Example130

3.3Signed Numbers132

3.3.1Negative Numbers133

3.3.2Addition and Subtraction135

3.3.3Adder and Subtractor Unit138

3.3.4RadixComplement Schemes139

3.3.5Arithmetic Overflow143

3.3.6Performance Issues145

3.4Fast Adders145

3.4.1CarryLookahead Adder146

3.5Design of Arithmetic Circuits Using CAD

Tools151

3.5.1Design of Arithmetic Circuits Using

Schematic Capture151

3.5.2Design of Arithmetic Circuits Using

Verilog152

3.5.3Using Vectored Signals155

3.5.4Using a Generic Specification156

3.5.5Nets and Variables in Verilog158

3.5.6Arithmetic Assignment

Statements159

3.5.7Module Hierarchy in Verilog

Code163

3.5.8Representation of Numbers in Verilog

Code166

3.6Multiplication167

3.6.1Array Multiplier for Unsigned

Numbers167

3.6.2Multiplication of Signed

Numbers169

3.7Other Number Representations170

3.7.1FixedPoint Numbers170

3.7.2FloatingPoint Numbers172

3.7.3BinaryCodedDecimal

Representation174

3.8Examples of Solved Problems178

Problems184

References188

Chapter 4CombinationalCircuit Building

Blocks189

4.1Multiplexers190

4.1.1Synthesis of Logic Functions Using Multiplexers193

4.1.2Multiplexer Synthesis Using Shannons

Expansion196

4.2Decoders201

4.2.1Demultiplexers203

4.3Encoders205

4.3.1Binary Encoders205

4.3.2Priority Encoders205

4.4Code Converters208

4.5Arithmetic Comparison Circuits208

4.6Verilog for Combinational Circuits210

4.6.1The Conditional Operator210

4.6.2The IfElse Statement212

4.6.3The Case Statement215

4.6.4The For Loop221

4.6.5Verilog Operators223

4.6.6The Generate Construct228

4.6.7Tasks and Functions229

第3章數的表示和算術電路121

3.1數位表示法122

3.1.1無符號整數122

3.1.2八進制數和十六進制數的

表示123

3.2無符號數的加法125

3.2.1全加器的分解129

3.2.2行波進位加法器129

3.2.3設計實例130

3.3有符號數132

3.3.1負數133

3.3.2加法和減法135

3.3.3加法器和減法器單元138

3.3.4基數補碼方案139

3.3.5算術溢出143

3.3.6性能問題145

3.4快速加法器145

3.4.1超前進位加法器146

3.5用CAD工具設計算術電路151

3.5.1用原理圖編輯工具設計算術

電路151

3.5.2用Verilog設計算術電路152

3.5.3用向量信號155

3.5.4用自動生成語句156

3.5.5Verilog中的線網和變數158

3.5.6算術賦值語句159

3.5.7Verilog中的模組層次化163

3.5.8Verilog中數的表示166

3.6乘法167

3.6.1無符號數的陣列乘法167

3.6.2有符號數的乘法169

3.7其他數的表示170

3.7.1定點數170

3.7.2浮點數172

3.7.3二進制編碼的十進制數

表示174

3.8問題求解案例178

習題184

參考文獻188

第4章組合電路構件塊189

4.1多路選擇器190

4.1.1用多路選擇器進行邏輯函式

綜合193

4.1.2用香農展開進行多路選擇器

綜合196

4.2解碼器201

4.2.1多路分解器203

4.3編碼器205

4.3.1二進制編碼器205

4.3.2優先編碼器205

4.4碼制轉換器208

4.5算術比較電路208

4.6用Verilog表示組合電路210

4.6.1條件操作符210

4.6.2ifelse語句212

4.6.3case語句215

4.6.4for循環語句221

4.6.5Verilog操作符223

4.6.6生成結構228

4.6.7任務和函式229

4.7Concluding Remarks232

4.8Examples of Solved Problems233

Problems243

References246

Chapter 5FlipFlops, Registers, and

Counters247

5.1Basic Latch249

5.2Gated SR Latch251

5.2.1Gated SR Latch with NAND

Gates253

5.3Gated D Latch253

5.3.1Effects of Propagation Delays255

5.4EdgeTriggered D FlipFlops256

5.4.1MasterSlave D FlipFlop256

5.4.2Other Types of EdgeTriggered

D FlipFlops258

5.4.3D FlipFlops with Clear and

Preset260

5.4.4FlipFlop Timing Parameters263

5.5T FlipFlop263

5.6JK FlipFlop264

5.7Summary of Terminology266

5.8Registers267

5.8.1Shift Register267

5.8.2ParallelAccess Shift Register267

5.9Counters269

5.9.1Asynchronous Counters269

5.9.2Synchronous Counters272

5.9.3Counters with Parallel Load276

5.10Reset Synchronization278

5.11Other Types of Counters280

5.11.1BCD Counter280

5.11.2Ring Counter280

5.11.3Johnson Counter283

5.11.4Remarks on Counter Design283

5.12Using Storage Elements with CAD

Tools284

5.12.1Including Storage Elements in

Schematics284

5.12.2Using Verilog Constructs for Storage

Elements285

5.12.3Blocking and NonBlocking

Assignments288

5.12.4NonBlocking Assignments for

Combinational Circuits293

5.12.5FlipFlops with Clear

Capability293

5.13Using Verilog Constructs for Registers

and Counters295

5.13.1FlipFlops and Registers with

Enable Inputs300

5.13.2Shift Registers with Enable

Inputs302

5.14Design Example302

5.14.1Reaction Timer302

5.14.2Register Transfer Level (RTL)

Code309

5.15Timing Analysis of Flipflop

Circuits310

5.15.1Timing Analysis with Clock

Skew312

5.16Concluding Remarks314

5.17Examples of Solved Problems315

Problems321

References329

Chapter 6Synchronous Sequential

Circuits331

6.1Basic Design Steps333

6.1.1State Diagram333

4.7小結232

4.8問題求解案例233

習題243

參考文獻246

第5章觸發器、暫存器和計數器247

5.1基本鎖存器249

5.2門控SR鎖存器251

5.2.1用與非門實現的門控SR

鎖存器253

5.3門控D鎖存器253

5.3.1傳輸延時的影響255

5.4邊沿觸發的D觸發器256

5.4.1主從D觸發器256

5.4.2其他類型的邊沿觸發的

D觸發器258

5.4.3帶清零和置位的D觸發器260

5.4.4觸發器的時間參數263

5.5T觸發器263

5.6JK觸發器264

5.7術語小結266

5.8暫存器267

5.8.1移位暫存器267

5.8.2並行存取的移位暫存器267

5.9計數器269

5.9.1異步計數器269

5.9.2同步計數器272

5.9.3可並行置數的計數器276

5.10同步復位278

5.11其他類型的計數器280

5.11.1BCD計數器280

5.11.2環形計數器280

5.11.3約翰森（Johnson）計數器283

5.11.4計數器設計小結283

5.12CAD工具中存儲單元的使用284

5.12.1在原理圖中加入存儲

單元284

5.12.2用Verilog代碼實現存儲

單元285

5.12.3阻塞和非阻塞賦值288

5.12.4組合電路的非阻塞賦值293

5.12.5具有清零功能的觸發器293

5.13用Verilog代碼實現暫存器和

計數器295

5.13.1具有使能輸入的觸發器和

暫存器300

5.13.2具有使能輸入的移位

暫存器302

5.14設計案例302

5.14.1反應計時器302

5.14.2暫存器傳輸級（RTL）

代碼309

5.15觸發器電路的時序分析310

5.15.1有時鐘漂移的時序分析312

5.16小結314

5.17問題求解案例315

習題321

參考文獻329

第6章同步時序電路331

6.1基本設計步驟333

6.1.1狀態圖333

6.1.2State Table335

6.1.3State Assignment336

6.1.4Choice of FlipFlops and Derivation

of NextState and Output

Expressions337

6.1.5Timing Diagram339

6.1.6Summary of Design Steps340

6.2StateAssignment Problem344

6.2.1OneHot Encoding347

6.3Mealy State Model349

6.4Design of Finite State Machines Using

CAD Tools354

6.4.1Verilog Code for MooreType

FSMs355

6.4.2Synthesis of Verilog Code356

6.4.3Simulating and Testing the

Circuit358

6.4.4Alternative Styles of Verilog

Code359

6.4.5Summary of Design Steps When

Using CAD Tools360

6.4.6Specifying the State Assignment in

Verilog Code361

6.4.7Specification of Mealy FSMs Using

Verilog363

6.5Serial Adder Example363

6.5.1MealyType FSM for Serial

Adder364

6.5.2MooreType FSM for Serial

Adder367

6.5.3Verilog Code for the Serial

Adder370

6.6State Minimization372

6.6.1Partitioning Minimization

Procedure374

6.6.2Incompletely Specified FSMs381

6.7Design of a Counter Using the Sequential

Circuit Approach383

6.7.1State Diagram and State Table for a

Modulo8Counter383

6.7.2State Assignment384

6.7.3Implementation Using DType Flip

Flops385

6.7.4Implementation Using JKType Flip

Flops386

6.7.5Example—A Different Counter390

6.8FSM as an Arbiter Circuit393

6.9Analysis of Synchronous Sequential

Circuits397

6.10Algorithmic State Machine (ASM)

Charts401

6.11Formal Model for Sequential

Circuits405

6.12Concluding Remarks407

6.13Examples of Solved Problems407

Problems416

References420

Chapter 7Digital System Design421

7.1Bus Structure422

7.1.1Using TriState Drivers to Implement

a Bus422

7.1.2Using Multiplexers to Implement

a Bus424

7.1.3Verilog Code for Specification of Bus

Structures426

7.2Simple Processor429

7.3A BitCounting Circuit441

7.4ShiftandAdd Multiplier446

7.5Divider455

7.6Arithmetic Mean466

6.1.2狀態表335

6.1.3狀態分配336

6.1.4觸發器的選擇以及次態和

輸出表達式的推導337

6.1.5時序圖339

6.1.6設計步驟小結340

6.2狀態分配問題344

6.2.1單熱編碼347

6.3米利狀態模型349

6.4用CAD工具設計有限狀態機354

6.4.1摩爾型有限狀態機的Verilog

代碼355

6.4.2Verilog代碼的綜合356

6.4.3仿真和測試該電路358

6.4.4另一種風格的Verilog

代碼359

6.4.5用CAD工具的設計步驟

小結360

6.4.6在Verilog代碼中進行狀態

分配361

6.4.7用Verilog代碼來描述米利

有限狀態機363

6.5串列加法器舉例363

6.5.1串列加法器的米利型有限

狀態機364

6.5.2串列加法器的摩爾型有限

狀態機367

6.5.3串列加法器的Verilog

代碼370

6.6狀態化簡372

6.6.1化簡過程的劃分374

6.6.2不完全確定的有限狀態機381

6.7用時序電路方法設計計數器383

6.7.1模8計數器的狀態圖和

狀態表383

6.7.2狀態分配384

6.7.3用D觸發器實現385

6.7.4用JK觸發器實現386

6.7.5案例——一個不一樣的計數器390

6.8用作仲裁器電路的有限狀態機393

6.9同步時序電路分析397

6.10算法狀態機（ASM）圖401

6.11時序電路的形式化模型405

6.12小結407

6.13問題求解案例407

習題416

參考文獻420

第7章數字系統設計421

7.1匯流排結構422

7.1.1用三態驅動器實現匯流排422

7.1.2用多路選擇器實現匯流排424

7.1.3匯流排結構的Verilog代碼

描述426

7.2簡單處理器429

7.3位計數電路441

7.4移位相加實現的乘法器446

7.5除法器455

7.6算術平均466

7.7Sort Operation470

7.8Clock Synchronization and Timing

Issues478

7.8.1Clock Distribution478

7.8.2FlipFlop Timing Parameters481

7.8.3Asynchronous Inputs to

FlipFlops482

7.8.4Switch Debouncing483

7.9Concluding Remarks485

Problems485

References489

Chapter 8Optimized Implementation of

Logic Functions491

8.1Multilevel Synthesis492

8.1.1Factoring493

8.1.2Functional Decomposition496

8.1.3Multilevel NAND and NOR

Circuits502

8.2Analysis of Multilevel Circuits504

8.3Alternative Representations of Logic

Functions510

8.3.1Cubical Representation510

8.3.2Binary Decision Diagrams514

8.4Optimization Techniques Based on Cubical

Representation520

8.4.1A Tabular Method for

Minimization521

8.4.2A Cubical Technique for

Minimization529

8.4.3Practical Considerations536

8.5Concluding Remarks537

8.6Examples of Solved Problems537

Problems546

References549

Chapter 9Asynchronous Sequential

Circuits551

9.1Asynchronous Behavior552

9.2Analysis of Asynchronous Circuits556

9.3Synthesis of Asynchronous Circuits564

9.4State Reduction577

9.5State Assignment592

9.5.1Transition Diagram595

9.5.2Exploiting Unspecified NextState

Entries598

9.5.3State Assignment Using Additional

State Variables602

9.5.4OneHot State Assignment607

9.6Hazards608

9.6.1Static Hazards609

9.6.2Dynamic Hazards613

9.6.3Significance of Hazards614

9.7A Complete Design Example616

9.7.1The VendingMachine

Controller616

9.8Concluding Remarks621

9.9Examples of Solved Problems623

Problems631

References635

Chapter 10Computer Aided Design

Tools637

10.1Synthesis638

10.1.1Netlist Generation638

10.1.2Gate Optimization638

10.1.3Technology Mapping640

10.2Physical Design644

10.2.1Placement646

10.2.2Routing647

10.2.3Static Timing Analysis648

7.7排序操作470

7.8時鐘同步和時序問題478

7.8.1時鐘偏差478

7.8.2觸發器的時序參數481

7.8.3觸發器的異步輸入482

7.8.4開關抖動483

7.9小結485

習題485

參考文獻489

第8章邏輯函式的最佳化實現491

8.1多級綜合492

8.1.1提取公因子493

8.1.2函式分解496

8.1.3多級與非和或非電路502

8.2多級電路的分析504

8.3邏輯函式的替代表示510

8.3.1立方體表示510

8.3.2二進制決策圖514

8.4基於立方體表示的最佳化技術520

8.4.1化簡的列表法521

8.4.2立方體化簡技術529

8.4.3實際問題考慮536

8.5小結537

8.6問題求解案例537

習題546

參考文獻549

第9章異步時序電路551

9.1異步行為552

9.2異步電路分析556

9.3異步電路綜合564

9.4狀態化簡577

9.5狀態分配592

9.5.1轉移圖595

9.5.2未指定次態項的利用598

9.5.3用附加狀態進行的狀態

分配602

9.5.4單熱狀態分配607

9.6冒險608

9.6.1靜態冒險609

9.6.2動態冒險613

9.6.3冒險的意義614

9.7一個完整的設計實例616

9.7.1自動售貨機控制器616

9.8小結621

9.9問題求解案例623

習題631

參考文獻635

第10章計算機輔助設計工具637

10.1綜合638

10.1.1網表生成638

10.1.2門最佳化638

10.1.3技術映射640

10.2物理設計644

10.2.1布局646

10.2.2布線647

10.2.3靜態時序分析648

10.3Concluding Remarks650

References651

Chapter 11Testing of Logic Circuits653

11.1Fault Model654

11.1.1Stuckat Model654

11.1.2Single and Multiple Faults655

11.1.3CMOS Circuits655

11.2Complexity of a Test Set655

11.3Path Sensitizing657

11.3.1Detection of a Specific Fault659

11.4Circuits with Tree Structure661

11.5Random Tests662

11.6Testing of Sequential Circuits665

11.6.1Design for Testability665

11.7內建自測試669

11.7.1內建邏輯塊觀察器673

11.7.2簽字分析675

11.7.3邊界掃描676

11.8印製電路板676

11.8.1PCB測試678

11.8.2測試儀器679

11.9小結680

習題680

參考文獻683

附錄A數的表示和算術電路685

A.1Verilog代碼中的文檔686

A.2空白符686

A.3Verilog代碼中的信號686

A.4標識符687

A.5信號值、數值和參數687

A.5.1參數688

A.6線網和變數類型688

A.6.1線網688

A.6.2變數689

A.6.3存儲器690

A.7操作符690

A.8Verilog模組692

A.9門實例化694

A.10並行語句696

A.10.1連續賦值696

A.10.2使用參數697

A.11過程語句698

A.11.1Always和Initial塊698

A.11.2ifelse語句700

A.11.3語句順序701

A.11.4case語句702

A.11.5Casez和Casex語句703

A.11.6Loop語句704

A.11.7組合電路的阻塞和非阻塞賦值對比708

A.12使用子電路709

A.12.1子電路參數710

A.12.2生成能力712

A.13函式和任務713

A.14時序電路716

A.14.1門控D鎖存器717

A.14.2D觸發器717

A.14.3帶復位的觸發器718

A.14.4暫存器718

A.14.5移位暫存器720

A.14.6計數器721

A.14.7時序電路實例722

A.14.8摩爾型有限狀態機723

A.14.9MealyTypeFiniteState

Machines724

A.15GuidelinesforWritingVerilog

Code725

A.16ConcludingRemarks731

References731

AppendixBImplementation

Technology733

B.1TransistorSwitches734

B.2NMOSLogicGates736

B.3CMOSLogicGates739

B.3.1SpeedofLogicGateCircuits746

B.4NegativeLogicSystem747

B.5StandardChips749

B.5.17400SeriesStandardChips749

B.6ProgrammableLogicDevices753

B.6.1ProgrammableLogicArray

(PLA)754

B.6.2ProgrammableArrayLogic

(PAL)757

B.6.3ProgrammingofPLAsand

PALs759

B.6.4ComplexProgrammableLogic

Devices(CPLDs)761

B.6.5FieldProgrammableGate

Arrays764

B.7CustomChips,StandardCells,andGate

Arrays769

B.8PracticalAspects771

B.8.1MOSFETFabricationand

Behavior771

B.8.2MOSFETOnResistance775

B.8.3VoltageLevelsinLogicGates776

B.8.4NoiseMargin778

B.8.5DynamicOperationofLogic

Gates779

B.8.6PowerDissipationinLogic

Gates782

B.8.7Passing1sand0sThrough

TransistorSwitches784

B.8.8TransmissionGates786

B.8.9FaninandFanoutin

LogicGates788

B.8.10TristateDrivers792

B.9StaticRandomAccessMemory

(SRAM)794

B.9.1SRAMBlocksinPLDs797

B.10ImplementationDetailsforSPLDs,

CPLDs,andFPGAs797

B.10.1ImplementationinFPGAs804

B.11ConcludingRemarks806

B.12ExamplesofSolvedProblems807

Problems814

References823

Answers825

Index839

A.14.9米利型有限狀態機724

A.15編寫Verilog代碼的原則725

A.16小結731

參考文獻731

附錄B實現技術733

B.1電晶體開關734

B.2NMOS邏輯門736

B.3CMOS邏輯門739

B.3.1邏輯門電路的速度746

B.4負邏輯系統747

B.5標準晶片749

B.5.17400系列標準晶片749

B.6可程式邏輯器件753

B.6.1可程式邏輯陣列（PLA）754

B.6.2可程式陣列邏輯（PAL）757

B.6.3PLA和PAL的編程759

B.6.4複雜可程式邏輯陣列

（CPLDs）761

B.6.5現場可程式門陣列764

B.7定製晶片、標準單元和門陣列769

B.8實踐方面771

B.8.1MOSFET工藝和行為771

B.8.2MOSFET導通電阻775

B.8.3邏輯門中的電平值776

B.8.4噪聲容限778

B.8.5邏輯門的動態特性779

B.8.6邏輯門的功耗782

B.8.7通過電晶體開關傳輸

1和0784

B.8.8傳輸門786

B.8.9邏輯門的扇入和扇出788

B.8.10三態驅動器792

B.9靜態隨機存取存儲器（SRAM）794

B.9.1PLD中的SRAM塊797

B.10SPLD、CPLD和FPGA的實現

細節797

B.10.1FPGA實現804

B.11小結806

B.12問題求解案例807

習題814

參考文獻823

習題答案825

索引839