數字秒表
數字時鐘組成及功能：
1、分頻率器：用來產生100HZ計時脈衝；
2、十二或二十四進制計數器：對時進行計數；
3、六十進制計數器：對分和秒進行計數；
圖片4、六進制計數器：分別對秒十位和分十位進行計數；
5、十進制計數器：分別對秒個位和分個位進行計數；
6、掃描顯示解碼器：完成對7欄位數碼管顯示的控制。
設計內容及步驟：
1、根據電路持點，用層次設計概念。將此設計任務分成若干模組，規定每一模組的功能和各模組之間的接口，同時加深層次化設計概念；
2、軟體的元件管理深層含義，以及模組元件之間的連線概念，對於不同目錄下的同一設計，如何熔合；
3、適配劃分前後的仿真內容有何不同概念，仿真信號對象有何不同，有更深一步了解。熟悉了CPLD/FPGA設計的調試過程中手段的多樣化；
4、按適配劃分後的管腳定位，同相關功能塊硬體電路接口連線；
5、所有模組儘量採用VHDL語言設計。
電路圖
數字秒表分頻模組
將實驗箱提供的10MHz的時鐘脈衝分頻後變成100Hz的脈衝，該模組的VHDL設計代碼如下：
library ieee;
use ieee.std_logic_1164.all;
entity DIV105 is
port
(CLKIN: in std_logic;
CLKOUT: out std_logic
);
end;
architecture DEVIDER of DIV105 is
constant N:integer:=50000;
signal COUNTER:integer range 0 to N;
signal CLK:std_logic;
begin
process(CLKIN)
begin
if CLKIN'event and CLKIN="1" then
if COUNTER=N then
COUNTER<=0;
CLK<=not CLK;
else
COUNTER<=COUNTER+1;
end if;
end if;
end process;
CLKOUT<=CLK;
end;
計數模組
十進制計數模組的VHDL設計如下：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity count10 is
port(clr,start,clk: in bit;
cout: out bit;
daout: out std_logic_vector(3 downto 0));
end count10;
architecture a of count10 is
signal temp:std_logic_vector(3 downto 0);
begin
process(clk,clr)
begin
if clr="1" then
temp<="0000";
cout<="0";
elsif (clk'event and clk="1") then
if start="1" then
if temp>="1001" then
temp<="0000";
cout<="1";
else
temp<=temp+1;
cout<="0";
end if;
end if;
end if;
daout<=temp;
end process;
end a;
六進制計數模組的VHDL設計如下：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity count6 is
port(clr,start,clk: in bit;
daout: out std_logic_vector(3 downto 0);
cout: out std_logic);
end count6;
architecture a of count6 is
signal temp:std_logic_vector(3 downto 0);
begin
process(clk,clr)
begin
if clr="1" then
temp<="0000";
cout<="0";
elsif (clk'event and clk="1") then
if start="1" then
if temp>="0101" then
temp<="0000";
cout<="1";
else
temp<=temp+1;
cout<="0";
end if;
end if;
end if;
end process;
daout<=temp;
end a;
二十四進制計數模組的VHDL設計如下：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity count24 is
port(clr,start,clk: in bit;
cout: out bit;
daoutL: out std_logic_vector(3 downto 0);
daoutH: out std_logic_vector(3 downto 0));
end count24;
architecture a of count24 is
signal tempL:std_logic_vector(3 downto 0);
signal tempH:std_logic_vector(3 downto 0);
begin
process(clk,clr)
begin
if clr="1" then
tempL<="0000";
tempH<="0000";
cout<="0";
elsif (clk'event and clk="1") then
if start="1" then
if tempL>="1001" and tempH>="0000" then
tempL<="0000";
tempH<="0001";
cout<="0";
elsif tempL>="1001" and tempH>="0001" then
tempL<="0000";
tempH<="0010";
cout<="0";
elsif tempL>="0011" and tempH>="0010" then
tempL<="0000";
tempH<="0000";
cout<="1";
else
tempL<=tempL+1;
cout<="0";
end if;
end if;
end if;
daoutL<=tempL;
daoutH<=tempH;
end process;
end a;
顯示模組
顯示模組實現的功能是控制數碼管的段選和位選，該顯示模組用的是動態掃描顯示，掃描脈衝頻率是1000Hz.此模組的其它八組輸入端控制LED的段選位。
顯示模組1000HZ時鐘VHDL設計如下：
library ieee;
use ieee.std_logic_1164.all;
entity div0 is
port(clr,clk: in bit;q: buffer bit);
end div0;
architecture a of div0 is
signal counter:integer range 0 to 4999;
begin
process(clr,clk)
begin
if (clk="1" and clk'event) then
if clr="1" then
counter<=0;
elsif counter=4999 then
counter<=0;
q<= not q;
else
counter<=counter+1;
end if;
end if;
end process;
end a;
動態掃描模組的VHDL設計如下：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity SELTIME0 is
port(
clk:in std_logic;------掃描時鐘
secm1,secm0,sec1,sec0,min1,min0,h1,h0:in std_logic_vector(3 downto 0);-----分別為秒個位/時位；分個位/
daout:out std_logic_vector(3 downto 0);----------------輸出
sel:out std_logic_vector(2 downto 0));-----位選信號
end SELTIME0;
architecture fun of SELTIME0 is
signal count:std_logic_vector(2 downto 0);----計數信號
begin
sel<=count;
process(clk)
begin
if(clk'event and clk="1") then
if(count>="111") then
count<="000";
else
count<=count+1;
end if;
end if;
case count is
when"000"=>daout<= secm1;----百分之一秒位
when"001"=>daout<= secm0;----十分之一秒位
when"010"=>daout<= sec1;----秒個位
when"011"=>daout<= sec0;----十秒位
when"100"=>daout<=min1; ----分個位
when"101"=>daout<=min0;----十分位
when"110"=>daout<=h1;-----時個位
when others =>daout<=h0;----十時位
end case;
end process;
end fun;
數碼管驅動顯示VHDL代碼如下：
subdesign deled
(num[3..0]:input;
a,b,c,d,e,f,g:output;)
begin
table
num[3..0]=>a,b,c,d,e,f,g;
H"0" =>1,1,1,1,1,1,0;
H"1" =>0,1,1,0,0,0,0;
H"2" =>1,1,0,1,1,0,1;
H"3" =>1,1,1,1,0,0,1;
H"4" =>0,1,1,0,0,1,1;
H"5" =>1,0,1,1,0,1,1;
H"6" =>1,0,1,1,1,1,1;
H"7" =>1,1,1,0,0,0,0;
H"8" =>1,1,1,1,1,1,1;
H"9" =>1,1,1,1,0,1,1;
H"A" =>1,1,1,0,1,1,1;
H"B" =>0,0,1,1,1,1,1;
H"C" =>1,0,0,1,1,1,0;
H"D" =>0,1,1,1,1,0,1;
H"E" =>1,0,0,1,1,1,1;
H"F" =>1,0,0,0,1,1,1;
end table;
end;
報時模組
報時用蜂鳴器，每分鐘一次，持續1s
library ieee;
use ieee.std_logic_1164.all;
entity ALARM is
port(s1,s0:in std_logic_vector(3 downto 0);
clk:in std_logic;
q:out std_logic);
end ALARM;
architecture sss_arc of ALARM is
begin
process(clk)
begin
if clk'event and clk="1" then
if s1="0101" and s0="1001" then---當秒高位為5，低位為9
q<="1";-----高頻輸出為1
else
q<="0";
end if;
end if;
end process;
end sss_arc;
流程圖
整個數字秒表的設計流程圖如下：
圖片實驗結果和心得
總結
秒表的頂層設計經保存，編譯，管腳分配後，下載到FPGA晶片(EP1K100QC208—3)後，可以得到較為滿意的結果，感覺很欣慰。通過這次設計，對CPLD和FPGA有了進一步認識，希望在以後的學習和工作上有所套用。
