內容簡介
可程式通用邏輯門陣列晶片簡稱FPGA，與CPU，DSP並列為三大通用數字處理晶片，廣泛套用於通信、航空航天、醫療、國防軍工以及安防視頻監控等領域。通過本書的學習，讀者可以全面了解一顆FPGA晶片從設計、驗證到流片的全部開發過程。 本書共分10章，採取“總—分”的編排方式。第1章從架構的總體設計入題對FPGA進行介紹。第2~10章，分別對其中的各個重要模組逐一介紹，包括：時鐘網路、電源/地線網路和漏電流、可程式邏輯單元、可程式I/O模組、DDR存儲器接口、數字延時鎖定環、連線連線盒、互連線段長度分布以及配置模組。 本書適合從事積體電路設計的資深工程師、微電子專業高年級研究生以及從事微電子專業教學研究的教師和科研人員閱讀。本書還可以作為高等院校教授積體電路設計的輔助資料。
目錄
第1 章 FPGA 架構總體設計 ········································································· 1
1.1 FPGA 晶片研製流程·········································································· 1
1.2 FPGA 架構設計流程·········································································· 7
1.3 FPGA 規模和資源劃分 ····································································· 17
1.4 FPGA 中功能模組劃分 ····································································· 20
本章參考文獻 ······················································································ 26
第2 章 FPGA 中時鐘網路 ·········································································· 30
2.1 簡介 ···························································································· 30
2.2 FPGA CDN 建模 ············································································· 33
2.3 時鐘網路設計方法 ·········································································· 43
2.4 時鐘網路的靈活性 ·········································································· 48
2.5 路由級聯 ······················································································ 51
2.6 仿真實驗 ······················································································ 55
2.7 時鐘網路熱學建模 ·········································································· 61
2.8 仿真實驗 ······················································································ 62
本章參考文獻 ······················································································ 66
第3 章 FPGA 中電源/地線網路和漏電流 ······················································· 68
3.1 電源/地線網路 ··············································································· 68
3.2 IR-DROP 分析與最佳化 ········································································ 71
3.3 漏電流組成 ··················································································· 73
3.4 降低漏電流的方法 ·········································································· 74
3.5 基於VIA 分布的IR-DROP 分析 ··························································· 77
3.6 仿真實驗 ······················································································ 81
3.7 不均勻測試點的IR-DROP 求解 ··························································· 87
3.8 FPGA 電源網路IR-DROP 分析 ···························································· 89
本章參考文獻 ······················································································ 94
第4 章 FPGA 中可程式邏輯單元 ································································· 98
4.1 基於多路選擇器的邏輯單元 ······························································ 98
4.2 基於四輸入LUT 的可程式邏輯單元的設計 ·········································· 102
4.3 LUT 的模型與實現 ········································································ 103
4.4 LUT 的輸入數目K 的確定 ······························································· 106
4.5 進位邏輯 ····················································································· 109
4.6 基於查找表結構的FPGA 的不足 ······················································· 115
4.7 AIC 結構邏輯簇 ············································································ 117
4.8 基於AIC 結構FPGA 的邏輯簇 ························································· 120
4.9 面向AIC 的映射工具及結構評估平台 ················································ 124
4.10 結構特徵匹配的AIC 簇互連最佳化 ···················································· 125
4.11 仿真分析和比較 ·········································································· 131
本章參考文獻 ····················································································· 133
第5 章 FPGA 中可程式I/O 模組 ································································· 136
5.1 可程式I/O 系統結構 ······································································ 136
5.2 IOE 中的可程式輸入緩衝器設計 ······················································· 138
5.3 IOE 中的可程式輸出緩衝器設計 ······················································· 144
5.4 可程式I/O 的後端版圖設計······························································ 156
5.5 高可靠I/O 模組的後端版圖與測試 ····················································· 166
5.6 可程式I/O 的供電策略 ··································································· 172
5.7 全晶片IO 的ESD 技術 ··································································· 173
本章參考文獻 ····················································································· 179
第6 章 FPGA 中DDR 存儲器接口 ······························································ 182
6.1 DDR SDRAM 晶片的工作原理 ·························································· 182
6.2 FPGA 晶片中DDR 存儲器接口系統設計 ············································· 184
6.3 DDR 存儲器接口控制器的設計和驗證 ················································ 191
6.4 延時鎖相技術 ··············································································· 194
6.5 延時鎖定環電路的分析與對比 ·························································· 196
6.6 數字延時鎖定環電路的性能分析與最佳化 ·············································· 201
6.7 延時鎖定環線性模型與穩定性分析 ···················································· 205
本章參考文獻 ····················································································· 209
第7 章 FPGA 中數字延時鎖定環 ································································ 213
7.1 實現相移的全數字延遲鎖定環 ·························································· 213
7.2 數字控制延時鏈 ············································································ 215
7.3 時間數字轉換器 ············································································ 220
7.4 雙向移位計數器 ············································································ 221
7.5 鑒相器與鎖定邏輯 ········································································· 222
7.6 延遲鎖定環的版圖設計 ··································································· 224
7.7 延遲鎖定環環路的仿真 ··································································· 224
7.8 晶片的物理實現與測試平台 ····························································· 225
7.9 DDR 接口的數據通路的測試驗證 ······················································ 227
7.10 數字延時鎖定環的測試 ································································· 229
7.11 數字占空比矯正電路的測試 ···························································· 232
本章參考文獻 ····················································································· 234
第8 章 FPGA 中連線連線盒 ······································································ 236
8.1 引言 ··························································································· 236
8.2 問題分析 ····················································································· 237
8.3 利用模擬退火算法最佳化CB 拓撲結構 ·················································· 241
8.4 實驗及結果分析 ············································································ 246
8.5 連線開關盒的電路結構設計方法 ······················································· 251
本章參考文獻 ····················································································· 259
第9 章 FPGA 中互連線段長度分布 ····························································· 261
9.1 所提最佳化方法的基本思路 ································································ 261
9.2 以面積延時積最小為目標的最佳化 ······················································· 265
9.3 針對所提最佳化方法的討論 ································································ 268
9.4 設計實驗 ····················································································· 269
9.5 FPGA 晶片的設計實現 ···································································· 270
9.6 晶片的測試準備 ············································································ 272
本章參考文獻 ····················································································· 275
第10 章 FPGA 中的配置模組 ···································································· 277
10.1 配置系統的基本組成及特點 ···························································· 277
10.2 配置系統的功能需求 ···································································· 279
10.3 配置系統的硬體結構分析 ······························································ 281
10.4 配置碼流協定的結構及其對配置系統的影響 ······································· 286
10.5 配置系統總體框架 ······································································· 292
10.6 配置碼流協定的設計 ···································································· 297
10.7 配置系統的電路設計與實現 ···························································· 300
10.8 配置系統採用的驗證工具與方法 ······················································ 305
10.9 配置系統的驗證方案與功能點的抽取 ················································ 310
10.10 配置系統功能驗證平台的設計 ······················································· 312
10.11 配置系統驗證結果 ······································································ 319
本章參考文獻 ····················································································· 324
