教育背景
工學學士 (計算機科學與技術), 哈爾濱工業大學, 中國, 1985;工學碩士 (半導體物理與器件), 哈爾濱工業大學, 中國, 1988;
工學博士 (機電控制及自動化), 哈爾濱工業大學, 中國, 1996;
博士後, 浙江大學, 中國, 1999.
社會兼職
清華大學計算機科學與技術系: 研究生工作組長 (2000-2003);清華大學計算機科學與技術系EDA實驗室: 實驗室主任 (2000-2008);
ACM/IEEE ASP-DAC: 程式委員會委員 (2010-2011);
海淀區科委: 電子信息專家委員會委員 (2003-);
Joint Conference of Information Science: 程式委員會主席、指導委員會委員 (2007-2008);
日本早稻田大學: 訪問學者、客員教授 (2007-2009);
香港中文大學: 副研究員 (2003-2005).
研究概況
研究領域
積體電路物理設計理論與算法，數字系統設計自動化，
積體電路晶片設計；
現代最佳化算法及其套用
研究概況
主要從事積體電路布圖理論及算法研究，近年來在這些方面取得一系列研究成果。基於這些工作，成功地爭取到日本北九州政府及日本早稻田大學的支持，設立清華大學計算機系EDA日本北九州研究基地，開展長期的國際合作研究。針對積體電路布圖規劃和布局問題，提出了基於平面T型劃分的角模組序列布圖表示理論，包括數據結構、包含最優解的布圖表示及其理論、無冗餘可遍歷的解變換三路線模型等，已經成為該領域有重要影響的工作之一。零死區固定框線布圖表示及方程求解算法的提出，是一項重要的理論及技術突破。
結合積體電路物理設計中組合最佳化問題的研究，提出了既有全局平滑又有局部平滑機制的解空間平滑最佳化算法。結合積體電路布局問題，提出了最小自由度優先的布局算法，是迄今為止世界上最快的固定框線布局算法，並已被成功套用在三維裝箱、FPGA規劃等方面。
在模擬電路物理設計和數模混合SOC電路物理設計方向上，提出了基於信號流的布圖方法以及模擬電路布圖約束自動提取算法。還提出了針對熱效應的模擬電路失配模型、數模混合電路布局的快速噪聲模型、及考慮熱效應的模擬電路布圖算法。這些研究成果已轉讓至日本精工、Jedat等公司，並成功套用在其EDA產品中。
針對具有異構資源的FPGA布圖問題、2.5D積體電路布圖問題、3D積體電路布圖及互連最佳化問題、熱問題、多電壓布圖問題等研究難點，提出了一系列相應的最佳化方法。針對非直角互連的X結構和Y結構的布圖問題，提出了新的布圖規劃表示模型和精確的互連估計模型。此外，還提出了指令定製的最佳化算法以及體系結構探索算法。
研究課題
清華大學與日本早稻田大學合作項目: 系統晶片及其設計自動化研究 (2006-);清華大學與日本東芝公司合作項目: 模擬電路物理設計研究 (2007-2010);
國家自然科學基金重點項目: 可程式可重構SOC晶片系統結構及關鍵技術 (2006-2008);
國家自然科學基金項目: 解空間平滑及其在片上系統布圖規劃和互連資源規劃中的套用 (2005-2007);
國家自然科學基金重大研究計畫項目: 數模混合片上系統布圖規劃與布局算法 (2004-2006);
國家自然科學基金與香港研究資助局聯合項目: 基於最小自由度優先的最佳化算法及其套用研究 (2003-2005);
清華大學與日本精工、Jedat合作項目: 模擬電路布圖研究 (2002-2005);
國家自然基金國際合作重點項目: 國際SOC 晶片設計中心 (2001-2004).
科研成果
獎勵與榮譽
北京市科學技術二等獎——超深亞微米SOC物理級CAD關鍵技術及其套用 (2007);教育部國家自然科學二等獎——超大規模積體電路物理級最佳化和驗證問題基礎研究 (2006);
清華大學研究生教育管理“林楓獎”一等獎: (2002).
學術成果
[1] Xu He, Sheqin Dong, Yuchun Ma, Signal Through-the-Silicon Via Planning and Pin Assignment for Thermal and Wire Length Optimization in 3D ICs, Integration, the VLSI Journal. 2010[2] Bei Yu(*), Sheqin Dong, et al, Voltage and Level-Shifter Assignment Driven Floorplanning，IEICE Transaction on Fundamentals of Electronics, Communications and Computer Sciences,Vol. E92-A, No.12, Dec.2009
[3] Yaoguang Wei, Sheqin Dong, Xianlong Hong, APWL-Y:an accurate and efficient wirelength estimation technique for hexagon/triangle placement, Integration, the VLSI Journal, Integration, the VLSI Journal, 40 (2007), p406-419
[4] Chen S, Dong SQ, Hong XL, Yici Cai, Chung-Kuan Cheng, Jun Gu, “VLSI block placement with alignment constraints”, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS 53 (8): 622-626 AUG 2006
[5] Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu, “An Integrated Floorplanning with an Efficient Buffer Planning Algorithm”, IEEE Transactions on CAD of Integrated Circuits and Systems, Vol. 24 (No. 4) (2005)
[6] Xianlong Hong, Sheqin Dong, Gang Huang, Yici Cai, C.K. Cheng, Jun Gu, “Non-slicing Floorplan and Placement using Corner Block List Topological Representation”, IEEE Transaction on CAS, Vol. 51 (No. 5) (2004), pp228-233
[7] Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu, “Stairway Compaction using Corner Block List and Its Applications with Rectilinear Blocks”, ACM Transactions on Design Automation of Electronic Systems, Vol. 9 (No. 2) (2004), p199-211
[8] Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu, “Floorplanning with Abutment Constraints Based on Corner Block List”, Integration, the VLSI Journal, Vol. 31 (No. 1) (2001), p65-77
[9] Sheqin Dong, Xianlong Hong, Song Chen, Xing Qi, Ruijie Wang, “VLSI Module Placement with Preplaced Modules and Considering Congestion Using Solution Space Smoothing”, IEICE Transactions on Fundamental of Electronics, Communications and Computer Science, Vol. E86-A, (No.12) (2003), pp3136-3147
[10] Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu, “VLSI Floorplanning with Boundary Constraints Using Corner Block List Representation”, IEICE Transactions on Fundamental of Electronics, Communications and Computer Science, Vol. E84A (No. 11) (2001), p2697-2704
[11] Bei Yu, Sheqin Dong, et al, Floorplanning and Topology Generation for Application-Specific Network-on-Chip，ACM/IEEE ASP-DAC 2010,
[12] Ou He, Sheqin Dong, Jinian Bian, Satoshi Goto, C.K.Cheng, Bus Via Reduction Based on Floorplan Revising, ACM/IEEE GLSVLSI Rhode Island, USA,May 16-18, 2010
[13] Tao Lin, Sheqin Dong, Bei Yu, Song Chen, Satoshi Goto, A Revisit to Voltage Partitioning Problem, ACM/IEEE GLSVLSI Rhode Island, USA,May 16-18, 2010
[14] Wentao Sui, Sheqin Dong, Jinian Bian, Wirelength-Driven Force-Directed 3D FPGA Placement,ACM/IEEE GLSVLSI Rhode Island, USA,May 16-18, 2010
[15] Wenxu Sheng, Sheqin Dong, Yuliang Wu, Satoshi Goto, Fixed Outline Multi-Bend Bus Driven Floorplanning,ACM/IEEE ISQED 2010, USA,
[16] Xu He, Sheqin Dong,Simultaneous Buffer and Interlayer Via Planning for 3D Floorplanning, ACM/IEEE ISQED 2009, USA, pp740-745
[17] Ou He, Sheqin Dong, Jinian Bian, Satoshi Goto, C.K. Cheng, A Novel Fixed outline Floorplanner with Zero Deadspace for Hierarchical Design, ACM/IEEE International conference on CAD, 2008, USA,pp16-23
[18] Jiayi Liu, Sheqin Dong, Xianlong Hong, Yibo Wang (Tsinghua Univ., China), Satoshi Goto (Waseda Univ., Japan), Symmetry Constraint based on Mismatch Analysis for Analog Layout in SOI Technology, The 13th IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC2008), Korean, January,2008
[19] Jiayi Liu, Sheqin Dong, Yuchun Ma, Di Long, Xianlong Hong, “Thermal-driven Symmetry Constraint for Analog Layout with CBL Representation” The 12th IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC2007), Yokohama, Japan, 2007.1
[20] Hongjie Bai, Sheqin Dong, Xianlong Hong, Congestion driven buffer planning for X-Architecture, ACM/IEEE ISQED 2007, USA,pp835-840
[21] Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto, “Fast Custom Instruction Identification Algorithm based on Basic Convex Pattern Model for Supporting ASIP Automated Design”, IEICE Trans. Fundamentals, Vol. E91-A, No.6, pp. 1478-1487, June 2008.
[22] Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto, “Exploring Partitions based on Search Space Smoothing for Heterogeneous Multiprocessor System”, IEICE Trans. Fundamentals, Special Section on Nonlinear Theory and its Applications, Vol. E91-A, No.6, pp.2456-2464, Sep.2008.
[23] Hong Xianlong, Ma Yuchun, Dong Sheqin, Cai Yici, C.K. Cheng, Jun Gu, “A Floorplanning Representation Corner Block List and The Corner Block List Based Floorplanning Algorithm with Boundary Constraint”, SCIENCE IN CHINA (Series F), Vol. 47 (No. 1) (2004), p1-19
[24] Song Chen, X. Hong, S. Dong, Y. Ma, Y. Cai, C.K. Cheng, J. Gu, “A Buffer Planning Algorithm for Chip-Level Floorplanning”, SCIENCE IN CHINA SERIES F-INFORMATION SCIENCES 47 (6): 763-776 DEC 2004
[25] Yuchun Ma, Xianlong Hong, Sheqin Dong, C.K.Cheng, Jun Gu, “General Floorplans with L/T-shaped blocks using corner block list”, Journal of Computer Science and Technology vol.21, no. 6, Nov,2006 pp.922-926
[26] Dong Sheqin, Hong Xianlong, Wu Youliang, Gu Jun, “Deterministic VLSI Block Placement Algorithm Using Less Flexibility First Principle”, Journal of Computer Science and Technology (JCST), Vol. 18 (No. 6) (2003), p739-746
[27] Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, C-K Cheng, Jun Gu, “Fast Evaluation of Bounded Slice-line Grid”, Journal of Computer Science and Technology (JCST), Vol. 19 (No. 6) (2004), p973-980
[28] Sheqin Dong, Shuo Zhou, Xianlong Hong, Chungkuan Cheng, Jun Gu, Yici Cai, “An Optimum Placement Search Algorithm Based on Extended Corner Block List”, Journal of Computer Science and Technology (JCST), Vol. 17 (No. 6) (2002), p699-707
[29] Di Long; Xianlong Hong; Sheqin Dong;“Signal-path driven partition and placement for analog circuit” Design Automation, 2006. Asia and South Pacific Conference on 24-27 Jan. 2006 Page(s):6
[30] Renshen WANG, Sheqin DONG Xianlong HONG, “An Improved P-admissible Floorplan Representation Based on Corner Block List”, 2005.1, The 10th IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC2005), Shanghai, China, p1115-1118
[31] Jun Yuan, Sheqin Dong, Xianlong Hong, Yuliang Wu, “LFF Algorithm for Heterogeneous FPGA Floorplanning”, 2005.1, The 10th IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC2005), Shanghai, China, p1123-1126
[32] Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, C-K Cheng, Jun Gu, “An Integrated Floorplanning with an Efficient Buffer Planning Algorithm”, 2003.3, ACM/SIGDA International Symposium on Physical Design, USA
[33] Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, C-K Cheng, Jun Gu, “Dynamic Global Buffer Planning Optimization Based on Detail Block Locating and Congestion Analysis”, 2003.6, IEEE/ACM 40th Design Automation Conference, Los Angeles, USA, p 806-811
[34] Shuo Zhou, Sheqin Dong, Xianlong Hong,Yici Cai, C-K Cheng, Jun Gu, “ECBL: An Extended Corner Block List with Solution Space including Optimum Placement”, 2001.3, ACM/SIGDA International Symposium on Physical Design, USA, pp150-155
[35] Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, C-K Cheng, Jun Gu, “Floorplanning with Abutment Constraints and L-Shaped/T-Shaped Blocks based on Corner Block List”, 2001.6, IEEE/ACM 38th Design Automation Conference, Las Vegas, USA, p770-775
[36] Xianlong Hong, Gamg Huang, Yici Cai, Sheqin Dong, Jiangchun Gu, C.K. Cheng, Jun Gu, “Corner Block List: An Effective and Efficient Topological Representation of Non-Slicing Floorplan”, 2000.11.5, IEEE/ACM International Conference on CAD, p8-12
