內容介紹
本書介紹了與計算機體系結構相關的各種主題。第1章到第5章介紹了計算機體系結構課程中的許多基本概念，包括：數據表示與算術運算、計算機組織、編程模型、處理器設計。第6章和7章分別討論了流水線和指令級並行性方法，它們都是影響現代處理器的重要因素。第8章到第10章介紹了各種存儲器系統的設計，包括存儲器層次結構、高速緩衝存儲器和虛擬存儲器。第11章討論了輸入/輸出系統。第12章介紹了多處理器系統。通過閱讀本書，讀者能夠迅速了解與計算機體系結構相關的各種知識，並將其套用到其他課程的學習和編程實踐中。本書內容全面，每章均提供了大量的實例和習題，是學習計算機體系結構課程的一本極佳教輔材料。
作品目錄
chapter i introd uctionl .l purpose of this book
l .2 background assumed
l .3 material covered
l .4 chapter objectives
l .5 technological trends
l .6 measuring performance
l .7 speedup
l .8 amdahl's law
l.9 s
- solved problems
chapter 2 data representations and computer arithmetic
2. l objectives
2.2 from electrons to bits
2.3 binary representation of positive integers
2.4 arithmetic operations on positive integers
2.5 negative integers
2.6 floating-point numbers
2.7 s
solved problems
.chapter 3 computer organization
3. i objectives
3 .2 introduction
3 . 3 programs
3 .4 operating systems
3 .5 computer oganization
3.6 summary
solved problems
chapter 4 programming models
4. l objectives
4.2 introduction
4.3 types of instructions
4.4 stack-based architectures
4.5 general-purpose register architectures
4.6 comparing stack-based and general-purpose register
architectures
4.7 using stacks to implement procedure calls
4. 8 summary '
solved problems
chapter 5 processor design
5 .l objectives
5 .2 introduction
5 .3 instruction set architecture
5 .4 processor microarchitecture
5.5 s
solved problems
chapter 6 pipelining
6. l objectives
6 .2 introduction
6. 3 pipelining
6.4 instruction hazards and their impact on throughput
6.5 predicting execution time in pipelined processors
6.6 result forwarding (bypassing)
6.7 s
solved problems
chapter 7 instruction-level parallelism
7. l objectives
7 .2 introduction .
7.3 what is instruction-level parallelism?
7.4 limitations of instruction-level parallelism
7.5 superscalar processors
7.6 in-order versus out-of-order execution
7.7 register renaming '
7.8 vliw processors
7.9 compilation techniques for instruction-level palallelism
7.io s
solved problems
chapter 8 memory systems
8. l objectives
8 .2 introduction
8.3 latency, throughput and bandwidth
8.4 memory hierarchies
8.5 memory technologies
8.6 s
solved problems
chapter 9 caches
9. l objectives
9.2 introduction
9.3 data caches, instruction caches, and unified caches
9.4 describing caches
9.5 capacity
9.6 line length
9 .7 associativity
9.8 replacement policy
9.9 write-back versus write-through caches
9. io cache implementations
9.il tag arrays
9.12 hit/miss logic
9.13 data arrays
9. 14 categorizing cache misses
9.15 multilevel caches
9.16 s
solved problems
chapter io virtual nemory
l0.l objectives '
10.2 introduction
10.3 address translation
10.4 demand paging versus swapping
10.5 page tables
10.6 translation lookaside buffers
10.7 proteaion
10.8 caches and virtual memory
10.9 summary
solved problems
chapter il i/o
l l.l objectives
l l.2 introduction
1l.3 i/0 buses
l l.4 interrupts
l i.5 memory-mapped i/o
l l .6 direct memory aceess
i l.7 i/o devices
l l.8 disk systems
11.9 s
solved problems
chapter i 2 multiprocessors
12.1 objectives
12.2 introduction
12.3 speedup and performance
1 2.4 multiprocessor systems
12.5 message-passing systems
l 2.6 shared-memory systems
12.7 comparing message-passing and shared memory
12.8 summary
solved problems
index
