內容簡介
本書是近10年來惟一一本專門討論時序及時序驗證的專著,共分4章。本書全面討論了靜態時序驗證的各方面內容;全書不僅緊密結合電路圖和波形圖進行講解,還結合Synopsys公司的邏輯綜合和靜態時序分析工具講解如何通過命令加以實現;介紹過程中不僅從理論上闡述了延遲模型,而且注重實踐環節,引入了大量實際示
例加以深入探討。這種寫作風格將促進讀者能夠更全面、細緻地理解所講內容,因此本書十分適合自學。目錄
List of Figures
List of Tables
Preface
Acknowledgments
1 Introduction to Timing Verification
1.1 Introduction
1.2 Overview of Timing Verification
1.2.1 Intrinsic vs. Extrinsic Delay
1.2.2 Path Delay
1.3 Interface Timing Analysis
Elements of Timing Verification
2.1 Introduction
2.2 Clock Definitions
2.2.1 Gated Clocks
2.2.2 Clock Skews and Multiple Clock Groups
2.2.3 Multifrequency Clocks
2.2.4 Multiphase Clocks
2.3 More on STA
……
Timing in ASICA
4 Programmable Logic Based Design
A PrimeTime
B Pearl
C TimingDesigner
D Transistor-Level Timing Verification
References
Index
About the Author
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